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MRF89XA
3.11 Packet Mode
Similar to Buffered mode operation, in Packet mode the
NRZ data to/from the modulator or demodulator is not
directly accessed by the host microcontroller, but it is
stored in the FIFO and accessed through the SPI data
interface.
The MRF89XA’s packet handler also performs several
packet oriented tasks such as Preamble and Sync
word generation, CRC calculation/check, DC scram-
bling (whitening/dewhitening of data), address
filtering. This simplifies the software still further and
reduces microcontroller overhead by performing these
repetitive tasks within the MRF89XA itself.
Another important feature is the ability to fill and empty
the FIFO in Stand-by mode, ensuring optimum power
consumption and adding more flexibility to the
software. Figure 3-25 shows the interface diagram
during Packet Mode.
Note: Bit Synchronizer and Sync word recogni-
tion are automatically enabled in Packet
mode.
FIGURE 3-25:
PACKET MODE BLOCK DIAGRAM
MRF89XA
CONTROL
IRQ0
IRQ1
Data
RX
SYNC
RECOG.
PACKET
HANDLER
FIFO
(+SR)
SPI
CONFIG
CSCON
TX
Datapath
? 2010–2011 Microchip Technology Inc.
Preliminary
DATA
CSDAT
SCK
SDI
SDO
DS70622C-page 81
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